Performs all integer arithmetic (add, subtract, multiply) and logical operations (AND, OR, NOT, XOR). Core execution engine for most instructions.
Handles floating-point arithmetic (decimals). Essential for scientific computing, 3D graphics, physics simulations, and audio/video processing.
Directs the operation of the processor. Fetches instructions from RAM, decodes them, and signals the ALU, FPU, and registers to execute the correct operation.
Guesses which branch of conditional code will execute next, pre-loading instructions before the condition resolves. Critical for pipeline efficiency.
Fastest and smallest memory. Split into instruction cache (L1i) and data cache (L1d). Directly feeds the ALU and FPU with minimal latency (typically 4–5 cycles).
Larger than L1 but slower. Acts as a second-level buffer between the core and the shared L3 cache. Typically 256KB–1MB per core.
Shared across all cores on the die. Much larger (8–64MB+) but higher latency. Reduces expensive RAM accesses by keeping frequently used data on-chip.
Integrated directly on modern CPUs, the PCIe controller manages high-speed communication to GPUs, NVMe SSDs, and other expansion devices — bypassing the chipset for lower latency.
Intel's socket design where pins are on the motherboard, not the CPU. The CPU has flat gold contact pads. Less fragile CPU-side; pins on socket are delicate.
Metal lid covering the CPU die. Spreads heat from the tiny die to the larger surface area where the cooler mounts. Thermal paste fills the microscopic gap between IHS and cooler.